RegViz: Visualize CACHE_DBG

Espressif Systems /ESP32-S2 /EXTMEM /CACHE_DBG_STATUS0

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Interpret as CACHE_DBG_STATUS0

Description

Fields

IBUS0_ACS_MSK_ICACHE_ST	The bit is used to indicate interrupt by cpu access icache while the ibus0 is disabled or icache is disabled which include speculative access.
IBUS1_ACS_MSK_ICACHE_ST	The bit is used to indicate interrupt by cpu access icache while the ibus1 is disabled or icache is disabled which include speculative access.
IBUS2_ACS_MSK_ICACHE_ST	The bit is used to indicate interrupt by cpu access icache while the ibus2 is disabled or icache is disabled which include speculative access.
IBUS0_ACS_CNT_OVF_ST	The bit is used to indicate interrupt by ibus0 counter overflow.
IBUS1_ACS_CNT_OVF_ST	The bit is used to indicate interrupt by ibus1 counter overflow.
IBUS2_ACS_CNT_OVF_ST	The bit is used to indicate interrupt by ibus2 counter overflow.
IBUS0_ACS_MISS_CNT_OVF_ST	The bit is used to indicate interrupt by ibus0 miss counter overflow.
IBUS1_ACS_MISS_CNT_OVF_ST	The bit is used to indicate interrupt by ibus1 miss counter overflow.
IBUS2_ACS_MISS_CNT_OVF_ST	The bit is used to indicate interrupt by ibus2 miss counter overflow.
IBUS0_ABANDON_CNT_OVF_ST	The bit is used to indicate interrupt by ibus0 abandon counter overflow.
IBUS1_ABANDON_CNT_OVF_ST	The bit is used to indicate interrupt by ibus1 abandon counter overflow.
IBUS2_ABANDON_CNT_OVF_ST	The bit is used to indicate interrupt by ibus2 abandon counter overflow.
IC_PRELOAD_MISS_CNT_OVF_ST	The bit is used to indicate interrupt by pre-load miss counter overflow.
IC_PRELOAD_CNT_OVF_ST	The bit is used to indicate interrupt by pre-load counter overflow.
IC_SYNC_SIZE_FAULT_ST	The bit is used to indicate interrupt by manual sync configurations fault.
IC_PRELOAD_SIZE_FAULT_ST	The bit is used to indicate interrupt by manual pre-load configurations fault.
ICACHE_REJECT_ST	The bit is used to indicate interrupt by authentication fail.
ICACHE_SET_PRELOAD_ILG_ST	The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations.
ICACHE_SET_SYNC_ILG_ST	The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations.
ICACHE_SET_LOCK_ILG_ST	The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations.

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